FM21L16 - 128Kx16 FRAM
along with a new column address provides a page
mode write access.
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is being prepared for a
new access. Precharge is user-initiated by driving the
/CE signal high. It must remain high for at least the
minimum precharge time t
PC
.
Sleep Mode
The device incorporates a sleep mode of operation
which allows the user to achieve the lowest power
supply current condition. It enters a low power sleep
mode by asserting the /ZZ pin low. Read and write
operations must complete prior to the /ZZ pin going
low. Once /ZZ is low, all pins are ignored except the
/ZZ pin. When /ZZ is deasserted high, there is some
time delay (t
ZZEX
) before the user can access the
device.
If Sleep Mode is not used, the /ZZ pin should be tied
to V
DD
.
The data byte contains the write-protect settings. This
value will not be written to the memory array, so the
address is a don’t-care. Rather it will be held pending
the next cycle, which must be a write of the data
complement to the protection settings. If the
complement is correct, the write protect settings will
be adjusted. If not, the process is aborted and the
address sequence starts over. The data value written
after the correct six addresses will not be entered into
memory.
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector. The
data byte must be driven to the lower 8-bits of the
data bus, DQ(7:0). Setting a bit to 1 write protects the
corresponding sector; a 0 enables writes for that
sector. The following table shows the write-protect
sectors with the corresponding bit that controls the
write-protect setting.
Write Protect Sectors – 16K x16 blocks
Sector 7
1FFFFh – 1C000h
Sector 6
1BFFFh – 18000h
Sector 5
17FFFh – 14000h
Sector 4
13FFFh – 10000h
Sector 3
0FFFFh – 0C000h
Sector 2
0BFFFh – 08000h
Sector 1
07FFFh – 04000h
Sector 0
03FFFh – 00000h
The write-protect read address sequence follows:
1.
12555h *
2.
1DAAAh
3.
01333h
4.
0ECCCh
5.
000FFh
6.
1FF00h
7.
1DAAAh
8.
0ECCCh
9.
0FF00h
10. 00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 12555h.
The address sequence provides a very secure way of
modifying the protection. The write-protect sequence
has a 1 in 3 x 10
32
chance of randomly accessing
exactly the 1
st
six addresses. The odds are further
reduced by requiring three more write cycles, one that
requires an exact inversion of the data byte. A flow
chart of the entire write protect operation is shown in
Figure 2. The write-protect settings are nonvolatile.
The factory default: all blocks are unprotected.
Software Write Protection
The 128Kx16 address space is divided into 8 sectors
(blocks) of 16Kx16 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
To modify write protection, the system host must
issue six read commands, three write commands, and
a final read command. The specific sequence of read
addresses must be provided in order to access to the
write protect mode. Following the read address
sequence, the host must write a data byte that
specifies the desired protection state of each sector.
For confirmation, the system must then write the
complement of the protection byte immediately
following the protection byte. Any error that occurs
including read addresses in the wrong order, issuing a
seventh read address, or failing to complement the
protection value will leave the write protection
unchanged.
The write protect state machine monitors all
addresses, taking no action until this particular
read/write sequence occurs. During the address
sequence, each read will occur as a valid operation
and data from the corresponding addresses will be
driven onto the data bus. Any address that occurs out
of sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
Rev. 1.0
Sept. 2007
Page 5 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
