FM21L16 - 128Kx16 FRAM
16K x 16 block
Address Latch & Write Protect
16K x 16 block
Block & Row Decoder
16K x 16 block
16K x 16 block
A(16:0)
A(16:2)
16K x 16 block
16K x 16 block
A(1:0)
16K x 16 block
16K x 16 block
Column Decoder
CE
WE
UB, LB
OE
ZZ
2
I/O Latch & Bus Driver
Control
Logic
DQ(15:0)
Figure 1. Block Diagram
Pin Description
Pin Name
Type
A(16:0)
Input
/CE
Input
/WE
Input
/OE
/ZZ
Input
Input
DQ(15:0)
/UB
/LB
VDD
VSS
Rev. 1.0
Sept. 2007
I/O
Input
Input
Supply
Supply
Pin Description
Address inputs: The 17 address lines select one of 131,072 words in the FRAM array.
The lowest two address lines A(1:0) may be used for page mode read and write
operations.
Chip Enable input: The device is selected and a new memory access begins when /CE is
low and /ZZ is high. The entire address is latched internally on the falling edge of /CE.
Subsequent changes to the A(1:0) address inputs allow page mode operation when /CE
is low.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM21L16 to write the data on the DQ bus to the FRAM array. The falling edge of /WE
latches a new column address for page mode write cycles.
Output Enable: When /OE is low, the FM21L16 drives the data bus when valid read
data is available. Deasserting /OE high tri-states the DQ pins.
Sleep: When /ZZ is low, the device enters a low power sleep mode for the lowest supply
current condition. Since this input is logically AND’d with /CE, /ZZ must be high for
normal read/write operation. If unused, tie /ZZ to V
DD
.
Data: 16-bit bi-directional data bus for accessing the FRAM array.
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z
if /UB is high.
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z
if /LB is high.
Supply Voltage: 3.3V
Ground
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