/F Refresh Cycle
tRE
/RE
0, 2,3
tMSU
tRP
tMH
/F
Don’t Care or Indeterminate
NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don’t care.
2. /RE inactive cache reads may be performed in parallel with /F refresh cycles.
/RE-Only Refresh
tC
tRE
/RE
0,2,3
tRP
tASR
tRAH
A
Row
0-10
tNRS
tNRH
/CAL
,
0-3,P
/WE, /G, W/R
tMSU
tMH
/F
tSSR
tSHR
/S
0,1
Don’t Care or Indeterminate
NOTES: 1. All binary combinations of A must be refreshed every 64ms interval. A does not have to be cycled, but must remain valid
0-9
10
during row address setup and hold times.
2. /RE refresh is write cycle with no /CAL active cycle.
2-112
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
