QN8007B/8007LB
Figure 7: Timing for QN8007 as I2S Master and Receiver
Table 12: Timing for QN8007 as I2S Master and Receiver
SYMBOL
PARAMETER
I2S clock period
CONDITIONS
MIN
TYP
MAX UNIT
T
tLC
tHC
ts
330
120
120
10
ns
ns
ns
ns
ns
Clock low time
Clock high time
SD setup time
SD hold time
th
5
tdtr
tRC
tFC
WS delay time
Clock rise-time
Clock fall-time
10
5
ns
ns
ns
5
Rev 2.09 (11/09)
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