HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 14
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–5–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC3200U– PC3200U– PC3200U– PC3200U– PC3200U–
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
CCD [cycles]
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
t
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
20
60
60
40
40
00
37
41
28
28
50
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
RRDmin [ns]
RCDmin [ns]
RASmin [ns]
Module Density per Rank
tAS,
tAH,
t
t
CS [ns]
CH [ns]
t
t
DS [ns]
DH [ns]
36 - 40 Not used
41
42
43
44
45
46
t
t
t
t
t
RCmin [ns]
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
Not used
Internet Data Sheet
19
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
QIMONDA [ QIMONDA AG ]
