HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 15
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–6–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2700U– PC2700U– PC2700U–
PC2700U– PC2700U–
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
09
01
40
00
04
60
70
00
82
10
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
01
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
01
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
02
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
02
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
t
t
CK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
t
t
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
Internet Data Sheet
22
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
QIMONDA [ QIMONDA AG ]
