HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 13
AC Timing - Absolute Specifications for PC3200 and PC2700 (cont’d)
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition 1)
DDR333
Min.
Min.
Max.
Max.
Address and control input setup tIS
time
0.6
—
0.75
—
ns
ns
fast slew rate
3)4)5)6)8)
0.7
—
0.8
—
slow slew
rate
3)4)5)6)8)
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
Data-out low-impedance time
from CK/CK
tLZ
–0.7
2
+0.7
—
–0.7
2
+0.7
—
ns
Mode register set command cycle tMRD
time
tCK
DQ/DQS output hold time
Data hold skew factor
tQH
t
HP – tQH
—
t
HP – tQHS
—
ns
ns
tQHS
—
+0.50
—
+0.55
TSOPII
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active to Autoprecharge delay
Active to Precharge command
tRAP
tRAS
tRC
tRCD
40
—
tRCD
—
ns
70E+3 42
70E+3 ns
Active to Active/Auto-refresh
command period
55
—
60
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
15
—
65
—
18
—
72
—
ns
µs
ns
2)3)4)5)10)
2)3)4)5)
Average Periodic Refresh Interval tREFI
7.8
—
7.8
—
Auto-refresh to Active/Auto-
refresh command period
tRFC
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Precharge command period
Read preamble
tRP
15
—
18
—
ns
tCK
tCK
ns
tRPRE
tRPST
tRRD
0.9
0.40
10
1.1
0.60
—
0.9
0.40
12
1.1
0.60
—
Read postamble
Active bank A to Active bank B
command
2)3)4)5)
Write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
—
0.25
0
—
tCK
ns
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
Write preamble setup time
Write postamble
—
—
0.40
15
0.60
—
0.40
15
0.60
—
tCK
ns
Write recovery time
2)3)4)5)
Internal write to read command
delay
tWTR
2
—
1
—
tCK
2)3)4)5)
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
75
—
—
75
—
—
ns
Exit self-refresh to read command tXSRD
200
200
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
Internet Data Sheet
16
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
QIMONDA [ QIMONDA AG ]
