Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Parameter
Symbol –5
DDR400B
–6
Unit Note1)/ Test
Condition
DDR333
Min.
Max.
Min.
Max.
Address and control input setup time tIS
0.6
—
0.75
—
ns
ns
ns
tCK
Fast slew rate
3)4)5)6)8)
0.7
–0.7
2
—
0.8
–0.7
2
—
Slow slew rate
3)4)5)6)8)
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
Data-out low-impedance time from tLZ
CK/CK
+0.7
—
+0.7
—
Mode register set command cycle
time
tMRD
DQ/DQS output hold time
Data hold skew factor
tQH
t
HP – tQH
—
t
HP – tQHS
—
ns
ns
ns
ns
ns
tQHS
tRAP
tRAS
tRC
—
+0.50
—
—
+0.55
—
TSOPII 2)3)4)5)
2)3)4)5)
Active to Autoprecharge delay
Active to Precharge command
tRCD
40
tRCD
2)3)4)5)
2)3)4)5)
70E+3 42
70E+3
—
Active to Active/Auto-refresh
command period
55
—
60
2)3)4)5)
Active to Read or Write delay
tRCD
tREFI
15
—
65
—
18
—
72
—
ns
µs
ns
2)3)4)5)10)
2)3)4)5)
Average Periodic Refresh Interval
7.8
—
7.8
—
Auto-refresh to Active/Auto-refresh tRFC
command period
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Precharge command period
Read preamble
tRP
15
—
18
—
ns
tCK
tCK
ns
tRPRE
tRPST
tRRD
0.9
0.40
10
1.1
0.60
—
0.9
0.40
12
1.1
0.60
—
Read postamble
Active bank A to Active bank B
command
2)3)4)5)
Write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
—
0.25
0
—
tCK
ns
tCK
ns
tCK
ns
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
Write preamble setup time
Write postamble
—
—
0.40
15
2
0.60
—
0.40
15
1
0.60
—
Write recovery time
2)3)4)5)
Internal write to read command delay tWTR
—
—
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
75
—
75
—
2)3)4)5)
Exit self-refresh to read command
tXSRD
200
—
200
—
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥Σ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
.
t
8) Fast slew rate ≥ 1.0 V/ns, slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
Rev. 1.31, 2006-09
18
03292006-VN6D-DETI
QIMONDA [ QIMONDA AG ]
