Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Parameter
Symbol
Values
Typ.
Unit Note1)/Test Condition
Min.
Max.
8)
Input High (Logic1) Voltage VIH(DC)
Input Low (Logic0) Voltage VIL(DC)
V
REF + 0.15
—
—
—
V
V
V
DDQ + 0.3
V
8)
–0.3
–0.3
REF – 0.15
DDQ + 0.3
V
8)
Input Voltage Level, CK and VIN(DC)
V
CK Inputs
8)6)
Input Differential Voltage, CK VID(DC)
and CK Inputs
0.36
0.71
–2
—
—
—
V
DDQ + 0.6
V
7)
VI-Matching Pull-up Current VIRatio
to Pull-down Current
1.4
2
—
Input Leakage Current
II
µA
Any input 0 V ≤ VIN ≤ VDD; All
other pins not under test = 0 V
8)9)
Output Leakage Current
IOZ
–5
—
—
—
5
µA
DQs are disabled; 0 V ≤ VOUT
VDDQ
≤
8)
Output High Current, Normal IOH
Strength Driver
—
–16.2
—
mA
mA
V
OUT = 1.95 V 8)
OUT = 0.35 V8)
Output Low Current, Normal IOL
16.2
V
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ
.
.
5)
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
ID is the magnitude of the difference between the input level on CK and the input level on CK.
.
6)
V
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature
and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Rev. 1.31, 2006-09
14
03292006-VN6D-DETI
QIMONDA [ QIMONDA AG ]
