Preliminary Internet Data Sheet
HYI25DC512[16/80]0CE
512-Mbit Double-Data-Rate SDRAM
4
Electrical Characteristics
This chapter describes the electrical characteristics.
4.1
Operating Conditions
This chapter contains the operating conditions tables.
TABLE 15
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit Note/ Test
Condition
Min.
Typ. Max.
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
VIN, VOUT
VIN
–0.5
–1
—
—
—
—
—
—
1
V
DDQ + 0.5
V
—
—
—
—
—
—
—
—
+3.6
+3.6
+3.6
+85
+150
—
V
VDD
–1
V
VDDQ
TA
–1
V
–40
–55
—
°C
°C
W
mA
TSTG
PD
Power dissipation (per SDRAM component)
Short circuit output current
IOUT
—
50
—
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
TABLE 16
Input and Output Capacitances
Parameter
Symbol
Values
Typ.
Unit
Note/
Test Condition
Min.
Max.
1)
Input Capacitance: CK, CK
CI1
CdI1
CI2
2.0
—
—
—
—
—
—
—
3.0
0.25
3.0
0.5
5.0
0.5
pF
pF
pF
pF
pF
pF
1)
Delta Input Capacitance
1)
Input Capacitance: All other input-only pins
2.0
—
1)
Delta Input Capacitance: All other input-only pins CdIO
1)2)
1)
Input/Output Capacitance: DQ, DQS, DM
CIO
4.0
—
Delta Input/Output Capacitance: DQ, DQS, DM
CdIO
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C,
OUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
V
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
Rev. 0.7, 2006-12
18
11292006-TAIE-H645
QIMONDA [ QIMONDA AG ]
