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HYI25DC512160CE-5 参数 Datasheet PDF下载

HYI25DC512160CE-5图片预览
型号: HYI25DC512160CE-5
PDF下载: 下载PDF文件 查看货源
内容描述: 512 - Mbit的双数据速率SDRAM [512-Mbit Double-Data-Rate SDRAM]
分类和应用: 动态存储器
文件页数/大小: 30 页 / 1716 K
品牌: QIMONDA [ QIMONDA AG ]
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Preliminary Internet Data Sheet  
HYI25DC512[16/80]0CE  
512-Mbit Double-Data-Rate SDRAM  
TABLE 11  
Truth Table 2: Clock Enable (CKE)  
Current State CKE n-1  
CKEn  
Command n  
Action n  
Note  
Previous  
Cycle  
Current  
Cycle  
1)  
2)  
Self Refresh  
Self Refresh  
Power Down  
Power Down  
All Banks Idle  
All Banks Idle  
Bank(s) Active  
L
L
X
Maintain Self-Refresh  
Exit Self-Refresh  
L
H
L
Deselect or NOP  
X
L
Maintain Power-Down  
Exit Power-Down  
L
H
L
Deselect or NOP  
Deselect or NOP  
AUTO REFRESH  
Deselect or NOP  
See Table 12  
H
H
H
H
Precharge Power-Down Entry  
Self Refresh Entry  
Active Power-Down Entry  
L
L
H
1)  
VREF must be maintained during Self Refresh operation  
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200  
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.  
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.  
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.  
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.  
4. All states and sequences not shown are illegal or reserved.  
Rev. 0.7, 2006-12  
14  
11292006-TAIE-H645