Preliminary Internet Data Sheet
HYI25DC512[16/80]0CE
512-Mbit Double-Data-Rate SDRAM
%
$
ꢃꢍ
%
$
ꢀꢍ
ꢃꢍ
Uꢍ
$
ꢃ
ꢄꢍ
$
ꢃ
ꢃꢍ
$
ꢃ
ꢀꢍ
$
ꢉꢍ
$
ꢈꢍ
DWLQ
Zꢍ
$
ꢇꢍ
$
ꢆꢍ
$
ꢂꢍ
$
ꢁꢍ
$
ꢅꢍ
$
ꢄꢍ
ꢀꢍ
Zꢍ
$
ꢃꢍ
'6
Zꢍ
$
ꢀꢍ
'//ꢍ
Zꢍ
ꢍ
ꢀꢍ
UH
2
SH
U
Jꢍ
02
'
(ꢍ
JꢊꢍD
G
G
0
3
%
7
ꢀ
ꢁꢉꢀꢍ
TABLE 8
Extended Mode Register
Field
DLL
Bits
Type1)
Description
DLL Status
0
w
0B
1B
Enabled
Disabled
DS
1
Drive Strength
0B
1B
Normal
Weak
MODE
[12:3]
Operating Mode
00000000000BNormal Operation
Notes
1. A2 must be 0 to provide compatibility with early DDR devices
2. All other bit combinations are RESERVED.
1) w = write only register bit
Rev. 0.7, 2006-12
12
11292006-TAIE-H645
QIMONDA [ QIMONDA AG ]
