Preliminary Internet Data Sheet
HYI25DC512[16/80]0CE
512-Mbit Double-Data-Rate SDRAM
%
$
ꢃꢍ
%
$
ꢀꢍ
ꢀꢍ
Uꢍ
$
ꢃ
ꢄꢍ
$
ꢃ
ꢃꢍ
$
ꢃ
ꢀꢍ
UD LQ
Zꢍ
$
ꢉꢍ
$
ꢈꢍ
$
ꢇꢍ
$
ꢆꢍ
$
ꢂꢍ
&/
Zꢍ
$
ꢁꢍ
$
ꢅꢍ
7ꢍ
$ꢄꢍ
$
%
ꢃꢍ
/ꢍ
$ꢀꢍ
ꢍ
%
ꢀꢍ
UH
2S
H
W
Jꢍ0
2'
(ꢍ
JꢊꢍD
G
G
Zꢍ
Zꢍ
0
3
%
7
ꢀ
ꢁꢈꢀꢍ
TABLE 6
Mode Register Definition
Field
BL
Bits
Type1) Description
Burst Length
[2:0]
W
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001B
010B
011B
2
4
8
BT
CL
3
Burst Type
See Table 7 for internal address sequence of low order address bits.
0 Sequential
1 Interleaved
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
2
3
110B 2.5
101B 1.5
Note: CL = 1.5 for DDR200 components only
Operating Mode
MODE [12:7]
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
1) W = write only register bit
Rev. 0.7, 2006-12
10
11292006-TAIE-H645
QIMONDA [ QIMONDA AG ]
