Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol Note
1)2)3)4)5)6)
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data
bus inputs are floating.
1)2)3)4)5)6)
Operating Bank Interleave Read Current
IDD7
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK
=
t
CK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); tFAW = tFAW(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address bus inputs are stable during deselects; Data bus is switching.
2. Timing pattern: see Detailed IDD7 timings shown below.
1)
2)
3)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V.
I
I
DD specifications are tested after the device is properly initialized.
DD parameter are specified with ODT disabled.
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for IDD , see Table 34.
6) Timing parameter minimum and maximum values for IDD current measurements are defined in Chapter 7.
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect.
IDD7 : Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC.IDD without violating tRRD.IDD and tFAW.IDD using a burst length of 4. Control and
address bus inputs are STABLE during DESELECTs. IOUT = 0 mA.
Timing Patterns for devices with 1KB page size
DDR2-533: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
DDR2-667: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
DDR2-800: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
DDR2-1066: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D
D D D
Timing Patterns for devices with 2KB page size
DDR2-533: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
DDR2-667: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
DDR2-800: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
DDR2-1066: A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D A4 RA4 D D D D A5 RA5 D D D D A6
RA6D D D D A7 RA7 D D D D
TABLE 34
Definition for IDD
Parameter
Description
LOW
Defined as VIN ≤ VIL.AC.MAX
HIGH
Defined as VIN ≥ VIH.AC.MIN
STABLE
FLOATING
SWITCHING
Defined as inputs are stable at a HIGH or LOW level
Defined as inputs are VREF = VDDQ / 2
Defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
Rev. 1.60, 2008-08
38
09262007-3YK7-BKKG
QIMONDA [ QIMONDA AG ]
