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HYI18T1G800C2C-3.7 参数 Datasheet PDF下载

HYI18T1G800C2C-3.7图片预览
型号: HYI18T1G800C2C-3.7
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 128MX8, 0.5ns, CMOS, PBGA60, PLASTIC, TFBGA-60]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 70 页 / 3976 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T1G[40/80/16]0C2[C/F](L)  
1-Gbit Double-Data-Rate-Two SDRAM  
7.2  
Component AC Timing Parameters  
TABLE 38  
DRAM Component Timing Parameter by Speed Grade – DDR2–1066  
Parameter  
Symbol  
DDR2–1066  
Unit  
Note1)2)3)4)5)  
6)7)  
Min.  
Max.  
8)  
DQ output access time from CK / CK  
CAS to CAS command delay  
Average clock high pulse width  
Average clock period  
tAC  
–350  
2
+350  
ps  
tCCD  
nCK  
tCK.AVG  
ps  
9)10)  
11)  
tCH.AVG  
tCK.AVG  
0.48  
1875  
3
0.52  
7500  
CKE minimum pulse width ( high and low pulse tCKE  
nCK  
width)  
9)10)  
Average clock low pulse width  
tCL.AVG  
0.48  
0.52  
tCK.AVG  
nCK  
ns  
12)13)  
Auto-Precharge write recovery + precharge time tDAL  
WR + tnRP  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tDELAY  
tIS + tCK .AVG + tIH ––  
14)18)19)  
8)  
DQ and DM input hold time  
tDH.BASE  
tDIPW  
tDQSCK  
tDQSH  
75  
––  
ps  
DQ and DM input pulse width for each input  
DQS output access time from CK / CK  
DQS input high pulse width  
0.35  
–325  
0.35  
0.35  
tCK.AVG  
ps  
+325  
tCK.AVG  
tCK.AVG  
ps  
DQS input low pulse width  
tDQSL  
15)  
16)  
DQS-DQ skew for DQS & associated DQ signals tDQSQ  
175  
+ 0.25  
DQS latching rising transition to associated clock tDQSS  
– 0.25  
tCK.AVG  
edges  
17)18)19)  
16)  
DQ and DM input setup time  
tDS.BASE  
0
––  
ps  
DQS falling edge hold time from CK  
DQS falling edge to CK setup time  
tDSH  
tDSS  
tFAW  
0.2  
0.2  
35  
tCK.AVG  
tCK.AVG  
ns  
16)  
34)  
Four Activate Window for 1KB page size  
products  
34)  
20)  
Four Activate Window for 2KB page size  
products  
tFAW  
tHP  
45  
ns  
ps  
CK half pulse width  
Min(tCH.ABS  
,
__  
tCL.ABS  
)
8)21)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
tAC.MAX  
ps  
22)24)  
tIH.BASE  
tIPW  
200  
0.6  
ps  
Control & address input pulse width for each  
input  
tCK.AVG  
23)24)  
8)21)  
8)21)  
34)  
Address and control input setup time  
DQ low impedance time from CK/CK  
DQS/DQS low-impedance time from CK / CK  
MRS command to ODT update delay  
tIS.BASE  
tLZ.DQ  
tLZ.DQS  
tMOD  
125  
ps  
ps  
ps  
ns  
2 × tAC.MIN  
tAC.MIN  
0
tAC.MAX  
tAC.MAX  
12  
Rev. 1.60, 2008-08  
42  
09262007-3YK7-BKKG  
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