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HYI18T1G800C2C-3.7 参数 Datasheet PDF下载

HYI18T1G800C2C-3.7图片预览
型号: HYI18T1G800C2C-3.7
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 128MX8, 0.5ns, CMOS, PBGA60, PLASTIC, TFBGA-60]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 70 页 / 3976 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T1G[40/80/16]0C2[C/F](L)  
1-Gbit Double-Data-Rate-Two SDRAM  
TABLE 37  
Speed Grade Definition  
Speed Grade  
DDR2–667D  
–3S  
DDR2–533C  
–3.7  
Unit  
Note  
QAG Sort Name  
CAS-RCD-RP latencies  
Parameter  
5–5–5  
4–4–4  
tCK  
Symbol  
Min.  
Max.  
Min.  
Max.  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Period  
@ CL = 3  
tCK  
5
8
5
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
@ CL = 4  
@ CL = 5  
tCK  
3.75  
3
8
3.75  
3.75  
40  
8
tCK  
8
8
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
tRAS  
tRC  
tRCD  
tRP  
40  
55  
15  
15  
70k  
70k  
55  
15  
Row Precharge Time  
15  
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. .  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,  
input reference level is the crosspoint when in differential strobe mode. CKDQS RDQS  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ  
4) The output timing reference voltage level is VTT.  
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI  
.
Rev. 1.60, 2008-08  
41  
09262007-3YK7-BKKG  
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