Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 6
Address / Command Inputs Timing Parameters
tCK
tCH
tCL
CK
CK
tIS tIH
Input
Valid
Valid
Valid
= Don't Care
TABLE 8
Inputs Timing Parameters
Parameter
Symbol
- 6
- 7.5
Unit Note
min.
max.
min.
0.45
0.45
max.
0.55
1)
Clock high-level width
Clock low-level width
Clock cycle time
tCH
tCL
tCK
0.45
0.55
tCK
1)
0.45
6
0.55
–
0.55
–
tCK
1)2)
CL = 3
CL = 2
7.5
15
ns
12
–
–
1)3)4)5)
Address and control input setup time
Address and control input hold time
Address and control input pulse width
fast slew rate
slow slew rate
fast slew rate
slow slew rate
tIS
1.1
1.3
1.1
1.3
2.7
–
1.3
1.5
1.3
1.5
3.0
–
ns
1)3)6)
–
–
1)3)4)
tIH
–
–
ns
1)3)6)
–
–
1)7)
tIPW
–
–
ns
1) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
2) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes.
3) The transition time for address and command inputs is measured between VIH and VIL.
4) For command / address input slew rate ≥ 1V/ns.
5) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
6) For command / address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
7) This parameter guarantees device timing. It is verified by device characterization but are not subject to production test.
Rev.1.0, 2007-03
18
10242006-Y557-TZXW
QIMONDA [ QIMONDA AG ]
