Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.3
State Diagram
FIGURE 5
State Diagram
Deep
Power
Down
Power
On
Power
applied
DPDSX
Self
Refresh
Precharge
All Banks
DPDS
REFSX
REFS
REFA
Idle
MRS
MRS
EMRS
Auto
Refresh
All banks
precharged
CKEL
CKEH
Precharge
Power
Down
Active
Power
Down
ACT
CKEH
CKEL
Row
Active
Burst
Stop
WRITE
READ
BST
WRITE
READ
WRITEA
READA
READ
WRITE
READ
WRITEA
READA
READA
PRE
PRE
PRE
WRITE A
READ A
Precharge
PREALL
PRE
Automatic Sequence
Command Sequence
ACT = Active
BST = Burst Terminate
CKEL = Enter Power-Down
CKEH = Exit Power-Down
DPDS = Enter Deep Power-Down
DPDSX = Exit Deep Power-Down
EMRS = Ext. Mode Reg. Set
MRS = Mode Register Set
PRE = Precharge
PREALL = Precharge All Banks
REFA = Auto Refresh
REFSX = Exit Self Refresh
READ = Read w/o Auto Precharge
READA = Read with Auto Precharge
WRITE = Write w/o Auto Precharge
WRITEA = Write with Auto Precharge
REFS = Enter Self Refresh
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and commands
to control them, not all details. In particular situations involving more than one bank are not captured in full detail.
Rev.1.0, 2007-03
16
10242006-Y557-TZXW
QIMONDA [ QIMONDA AG ]
