Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4
Commands
TABLE 6
Command Overview
Command
CS RAS CAS WE
Address Note
1)2)
1)2)
1)3)
NOP
DESELECT
NO OPERATION
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
ACT
RD
ACTIVE (Select bank and row)
Bank / Row
Bank / Col
Bank / Col
X
1)4)
1)4)
1)5)
1)6)
1)7)8)
1)9)
READ (Select bank and column and start read burst)
WRITE (Select bank and column and start write burst)
BURST TERMINATE or DEEP POWER-DOWN
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH entry
MODE REGISTER SET
H
H
H
L
WR
L
BST
PRE
ARF
MRS
H
H
L
L
L
Code
L
H
L
X
L
L
Op-Code
1) CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER DOWN.
2) DESELECT and NOP are functionally interchangeable.
3) BA0, BA1 provide the bank address, and A0 - A12 provide the row address.
4) BA0, BA1 provide the bank address, A0 - A9 provide the column address; A10 HIGH enables the Auto Precharge feature (non persistent),
A10 LOW disables the Auto Precharge feature.
5) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER-DOWN if CKE is LOW. The BURST TERMINATE command is
defined for READ bursts with Auto Precharge disabled only; it is undefined (and should not be used) for read bursts with Auto Precharge
enabled, and for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged.A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other combinations of
BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.
TABLE 7
DM Operation
Name (Function)
DM
DQs Note
1)
Write Enable
L
Valid
1)
Write Inhibit
H
X
1) Used to mask write data provided coincident with the corresponding data
Address (BA0, BA1, A0 - A12) and command inputs (CKE, CS, RAS, CAS, WE) are all registered on the crossing of the positive
edge of CK and the negative edge of CK. Figure 6 shows the basic timing parameters, which apply to all commands and
operations.
Rev.1.0, 2007-03
17
10242006-Y557-TZXW
QIMONDA [ QIMONDA AG ]
