Data Sheet.
HY[B/E]18L512160BF-7.5
512-Mbit Mobile-RAM
1.4
Pin Definition and Description
TABLE 4
Pin Description
Ball
Type
Detailed Function
CLK
CKE
Input
Input
Clock: all inputs are sampled on the positive edge of CLK.
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, device input
buffers and output drivers. Taking CKE LOW provides:
•
•
•
PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle)
ACTIVE POWER-DOWN (row active in any bank)
SUSPEND (access in progress).
Input buffers, excluding CLK and CKE are disabled during power-down. Input buffers, excluding
CKE are disabled during SELF REFRESH.
CS
Input
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple memory banks. CS is considered part of the command
code.
RAS, CAS,
WE
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DQ0 - DQ15 I/O
Data Inputs/Output: Bi-directional data bus (16 bit)
LDQM,
UDQM
Input
Input/Output Mask: Input mask signal for WRITE cycles and output enable for READ cycles.
•
•
For WRITEs, DQM acts as a data mask when HIGH.
For READs, DQM acts as an output enable and places the output buffers in High-Z state when
HIGH (two clocks latency).
•
LDQM corresponds to the data on DQ0 - DQ7; UDQM to the data on DQ8 - DQ15.
BA0, BA1
A0 - A12
Input
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or
PRECHARGE command is being applied to. BA0, BA1 also determine which mode register will be
loaded during a MODE REGISTER SET command (MRS or EMRS).
Address Inputs: A0 - A12 define the row address during an ACTIVE command cycle. A0 -
A9 define the column address during a READ or WRITE command cycle. In addition, A10
(= AP) controls the Auto Precharge operation at the end of the burst read or write cycle.
During a PRECHARGE command, A10 (= AP), in conjunction with BA0, BA1, control
which bank(s) will be precharged:
•
•
if A10 is HIGH, all four banks will be precharged regardless of the state of BA0 and BA1
if A10 is LOW, BA0, BA1 define the bank to be precharged.
During MODE REGISTER SET commands, the address inputs hold the opcode to be loaded.
VDDQ
Supply I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity: VDDQ = 1.70
V to 1.95 V
VSSQ
VDD
VSS
Supply I/O Ground
Supply Power Supply: Power for the core logic and input buffers, VDD = 1.70 V to 1.95 V
Supply Ground
N.C.
–
No Connect
Rev. 1.22, 2006-12
7
01132005-06IU-IGVM
QIMONDA [ QIMONDA AG ]
