Data Sheet.
HY[B/E]18L512160BF-7.5
512-Mbit Mobile-RAM
FIGURE 40
WRITE with Auto Precharge Interrupted by WRITE
#,+
#OMMAND
!DDRESS
72ꢀ!0
./0
72)4%
./0
./0
./0
./0
./0
"ANK N
#OL B
"ANK M
#OL X
T72 ꢄBANK Nꢅ
$) Xꢆꢇ
T20 ꢄBANK Nꢅ
$) Xꢆꢇ
$) B
$) Bꢆꢇ
$) X
$) Xꢆꢇ
$1
ꢁ $ONgT #ARE
72ꢀ!0 ꢁ 7RITE WITH !UTO 0RECHARGEꢂ 72)4% ꢁ 7RITE WITH OR WITHOUT !UTO 0RECHARGE
"URST ,ENGTH ꢁ ꢃ IN THE CASE SHOWN
7RITE WITH !UTO 0RECHARGE TO BANK N IS INTERRUPTED BY SUBSEQUENT 7RITE TO BANK M
2.4.9
AUTO REFRESH and SELF REFRESH
The Mobile-RAM requires a refresh of all rows in a rolling interval. Each refresh is generated in one of two ways:
•
•
by an explicit AUTO REFRESH command
by an internally timed event in SELF REFRESH mode.
2.4.9.1
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
Mobile-RAM. The command is nonpersistent, so it must be
issued each time a refresh is required. A minimum row cycle
time (tRC) is required between two AUTO REFRESH
commands. The same rule applies to any access command
after the AUTO REFRESH operation. All banks must be
precharged prior to the AUTO REFRESH command.
The refresh addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during an
AUTO REFRESH command. The Mobile-RAM requires
AUTO REFRESH cycles at an average periodic interval of 7.8
µs (max.). Partial array mode has no influence on AUTO
REFRESH mode.
FIGURE 41
AUTO REFRESH Command
#,+
#+%
#3
ꢁ(IGHꢂ
2!3
#!3
7%
!ꢃꢄ!ꢅꢆ
"!ꢃꢇ"!ꢅ
ꢀ $ONgT #ARE
Rev. 1.22, 2006-12
39
01132005-06IU-IGVM
QIMONDA [ QIMONDA AG ]
