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HYE18L512160BF-7.5 参数 Datasheet PDF下载

HYE18L512160BF-7.5图片预览
型号: HYE18L512160BF-7.5
PDF下载: 下载PDF文件 查看货源
内容描述: DRAM的移动应用512 - Mbit的移动-RAM [DRAMs for Mobile Applications 512-Mbit Mobile-RAM]
分类和应用: 存储内存集成电路动态存储器时钟
文件页数/大小: 57 页 / 2043 K
品牌: QIMONDA [ QIMONDA AG ]
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Data Sheet.  
HY[B/E]18L512160BF-7.5  
512-Mbit Mobile-RAM  
TABLE 14  
Timing Parameters for PRECHARGE  
Parameter  
Symbol  
- 7.5  
Units  
Notes  
min.  
max.  
1)  
1)  
1)  
ACTIVE to PRECHARGE command period  
WRITE recovery time  
PRECHARGE command period  
tRAS  
tWR  
tRP  
45  
14  
19  
100k  
ns  
ns  
ns  
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:no. of clock cycles = specified  
delay / clock period; round up to next integer.  
2.4.8.2  
CONCURRENT AUTO PRECHARGE  
A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE command issued  
to a different bank.  
Figure 37 shows a READ with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge) to bank m.  
The READ to bank m will interrupt the READ to bank n, CAS latency later. The precharge to bank n will begin when the READ  
to bank m is registered.  
Figure 38 shows a READ with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge) to bank m.  
The precharge to bank n will begin when the WRITE to bank m is registered. DQM should be pulled HIGH two clock cycles  
prior to the WRITE to prevent bus contention.  
Figure 39 shows a WRITE with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge) to bank m.  
The precharge to bank n will begin tWR after the new command to bank m is registered. The last valid data-in to bank n is one  
clock cycle prior to the READ to bank m.  
Figure 40 shows a WRITE with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge) to bank  
m. The precharge to bank n will begin tWR after the WRITE to bank m is registered. The last valid data-in to bank n is one clock  
cycle prior to the WRITE to bank m.  
FIGURE 37  
READ with Auto Precharge Interrupted by READ  
#,+  
./0  
2$ꢀ!0  
./0  
2%!$  
./0  
./0  
./0  
./0  
#OMMAND  
!DDRESS  
"ANK N  
#OL B  
"ANK M  
#OL X  
#,ꢁꢃ  
T20 ꢇBANK Nꢈ  
$/ Bꢅꢆ  
$/ B  
$/ X  
$/ Xꢅꢆ  
$/ Xꢅꢃ  
$1  
ꢁ $ONgT #ARE  
2$ꢀ!0 ꢁ 2EAD WITH !UTO 0RECHARGEꢂ 2%!$ ꢁ 2EAD WITH OR WITHOUT !UTO 0RECHARGE  
#, ꢁ ꢃ AND "URST ,ENGTH ꢁ ꢄ IN THE CASE SHOWN  
2EAD WITH !UTO 0RECHARGE TO BANK N IS INTERRUPTED BY SUBSEQUENT 2EAD TO BANK M  
Rev. 1.22, 2006-12  
01132005-06IU-IGVM  
37  
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