Data Sheet.
HY[B/E]18L512160BF-7.5
512-Mbit Mobile-RAM
FIGURE 31
Clock Suspend Mode for WRITE Bursts
#,+
#+%
INTERNAL
CLOCK
./0
72)4%
./0
./0
./0
#OMMAND
!DDRESS
"A !ꢀ
#OL N
T#3,
T#3,
T#3,
$) N
$) Nꢅꢄ
$) Nꢅꢃ
$1
ꢂ $ONgT #ARE
"A !ꢀ #OL N ETCꢁ ꢂ "ANK !ꢀ #OLUMN N ETCꢁ
$/ N ETCꢁ ꢂ $ATA /UT FROM COLUMN N ETCꢁ
#, ꢂ ꢃ IN THE CASE SHOWN
#LOCK SUSPEND LATENCY T#3, IS ꢄ CLOCK CYCLE
2.4.6.3
WRITE - DQM Operation
DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be performed. The
generic timing parameters as listed in Table 13 also apply to this DQM operation. The write burst in progress is not affected
and will continue as programmed.
FIGURE 32
WRITE Burst - DQM Operation
#,+
./0
72)4%
./0
./0
./0
./0
#OMMAND
!DDRESS
$1-
"A !ꢀ
#OL N
$) N
$) Nꢆꢊ
$) Nꢆꢄ
$1
ꢁ $ONgT #ARE
"A !ꢀ #OL N ꢁ "ANK !ꢀ #OLUMN N
$) N ꢁ $ATA )N TO COLUMN N
"URST ,ENGTH ꢁ ꢂ IN THE CASE SHOWNꢃ
ꢄ SUBSEQUENT ELEMENTS OF $ATA )N ARE PROVIDED IN THE PROGRAMMED ORDER FOLLOWING
$) Nꢀ WITH THE FIRST ELEMENT ꢅ$) Nꢆꢇꢈ BEING MASKEDꢃ
$1- WRITE LATENCY IS ꢉ CLOCK CYCLESꢃ
Rev. 1.22, 2006-12
33
01132005-06IU-IGVM
QIMONDA [ QIMONDA AG ]
