Data Sheet.
HY[B/E]18L512160BF-7.5
512-Mbit Mobile-RAM
2.2.1.5
Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include:
•
•
•
the Partial Array Self Refresh (PASR, bits A0-A2))
the Temperature Compensated Self Refresh (TCSR, bits A3-A4))
the drive strength selection for the DQs (bits A5-A6).
The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will
retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle. Additionally, the controller must wait the specified time
before initiating any subsequent operation. Violating either of these requirements result in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
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TABLE 7
EMR Extended Mode Register (BA[1:0] = 10B)
Field
Bits
Type
Description
DS
[6:5]
w
Selectable Drive Strength
00B
01B
Full Drive Strength
Half Drive Strength
Note: All other bit combinations are RESERVED.
TCSR
PASR
[4:3]
[2:0]
w
w
Temperature Compensated Self Refresh
XX Superseded by on-chip temperature sensor (see text)
Partial Array Self Refresh
000B all banks
001B 1/2 array (BA1 = 0)
010B 1/4 array (BA1 = BA0 = 0)
101B 1/8 array (BA1 = BA0 = RA12 = 0)
110B 1/16 array (BA1 = BA0 = RA12 = RA11 = 0)
Note: All other bit combinations are RESERVED.
Rev. 1.22, 2006-12
12
01132005-06IU-IGVM
QIMONDA [ QIMONDA AG ]
