HY[B/E]18L256160B[C/F]X-7.5
256-Mbit Mobile-RAM
Functional Description
2
Functional Description
The 256-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.
It is internally configured as a quad-bank DRAM.
READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12
select the row). The address bits registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the Mobile-RAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command description and device operation.
2.1
Power On and Initialization
The Mobile-RAM must be powered up and initialized in a predefined manner (see Figure 3). Operational
procedures other than those specified may result in undefined operation.
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Figure 3
Power-Up Sequence and Mode Register Sets
Data Sheet
7
Rev. 1.11, 2007-01
07142005-CR47-RB2E
QIMONDA [ QIMONDA AG ]
