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HYE18L256160BFX-7.5 参数 Datasheet PDF下载

HYE18L256160BFX-7.5图片预览
型号: HYE18L256160BFX-7.5
PDF下载: 下载PDF文件 查看货源
内容描述: DRAM的移动应用256兆移动-RAM [DRAMs for Mobile Applications 256-Mbit Mobile-RAM]
分类和应用: 动态存储器
文件页数/大小: 48 页 / 1590 K
品牌: QIMONDA [ QIMONDA AG ]
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HY[B/E]18L256160B[C/F]X-7.5  
256-Mbit Mobile-RAM  
Overview  
1.4  
Pin Definition and Description  
Table 4  
Ball  
Pin Description  
Type  
Input  
Input  
Detailed Function  
CLK  
Clock: all inputs are sampled on the positive edge of CLK.  
CKE  
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals,  
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE  
POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-  
DOWN (row active in any bank) or SUSPEND (access in progress). Input buffers,  
excluding CLK and CKE are disabled during power-down. Input buffers, excluding CKE  
are disabled during SELF REFRESH.  
CS  
Input  
Input  
Chip Select: All commands are masked when CS is registered HIGH. CS provides for  
external bank selection on systems with multiple memory banks. CS is considered part of  
the command code.  
RAS, CAS,  
WE  
Command Inputs: RAS, CAS and WE (along with CS) define the command being  
entered.  
DQ0 - DQ15 I/O  
Data Inputs/Output: Bi-directional data bus (16 bit)  
LDQM,  
UDQM  
Input  
Input/Output Mask: input mask signal for WRITE cycles and output enable for READ  
cycles. For WRITEs, DQM acts as a data mask when HIGH. For READs, DQM acts as  
an output enable and places the output buffers in High-Z state when HIGH (two clocks  
latency).  
LDQM corresponds to the data on DQ0 - DQ7; UDQM to the data on DQ8 - DQ15.  
BA0, BA1  
A0 - A12  
Input  
Input  
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE  
or PRECHARGE command is being applied. BA0, BA1 also determine which mode  
register is to be loaded during a MODE REGISTER SET command (MRS or EMRS).  
Address Inputs: A0 - A12 define the row address during an ACTIVE command cycle. A0  
- A8 define the column address during a READ or WRITE command cycle. In addition,  
A10 (= AP) controls Auto Precharge operation at the end of the burst read or write cycle.  
During a PRECHARGE command, A10 (= AP) in conjunction with BA0, BA1 controls  
which bank(s) are to be precharged: if A10 is HIGH, all four banks will be precharged  
regardless of the state of BA0 and BA1; if A10 is LOW, BA0, BA1 define the bank to be  
precharged. During MODE REGISTER SET commands, the address inputs hold the op-  
code to be loaded.  
VDDQ  
Supply I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity:  
DDQ = 1.70V to 1.95V  
V
VSSQ  
VDD  
Supply I/O Ground  
Supply Power Supply: Power for the core logic and input buffers, VDD = 1.70V to 1.95V  
Supply Ground  
VSS  
N.C.  
No Connect  
Data Sheet  
6
Rev. 1.11, 2007-01  
07142005-CR47-RB2E