HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
#OMMAND
!DDRESS
$1
./0
72)4%
./0
./0
"34
./0
./0
"A !ꢉ
#OL N
$) N
$) Nꢓꢅ
$) Nꢓꢆ
ꢃ $ONgT #ARE
"A !ꢉ #OL N ꢃ "ANK !ꢉ #OLUMN N
$) N ꢃ $ATA )N TO COLUMN N
"URST ,ENGTH ꢃ ꢏ IN THE CASE SHOWNꢂ
ꢆ SUBSEQUENT ELEMENTS OF $ATA )N ARE WRITTEN IN THE PROGRAMMED ORDER FOLLOWING $) Nꢂ
4HE BURST IS TERMINATED AFTER THE ꢐRD DATA ELEMENTꢂ
Figure 30 Terminating a WRITE Burst
2.4.6.2
Clock Suspend Mode for WRITE Cycles
Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long
as CKE is registered LOW, the following internal clock pulse(s) will be ignored and no data will be captured, as
shown in Figure 31.
#,+
#+%
INTERNAL
CLOCK
./0
72)4%
./0
./0
./0
#OMMAND
!DDRESS
"A !ꢉ
#OL N
T#3,
T#3,
T#3,
$) N
$) Nꢓꢅ
$) Nꢓꢆ
$1
ꢃ $ONgT #ARE
"A !ꢉ #OL N ETCꢂ ꢃ "ANK !ꢉ #OLUMN N ETCꢂ
$/ N ETCꢂ ꢃ $ATA /UT FROM COLUMN N ETCꢂ
#, ꢃ ꢆ IN THE CASE SHOWN
#LOCK SUSPEND LATENCY T#3, IS ꢅ CLOCK CYCLE
Figure 31 Clock Suspend Mode for WRITE Bursts
Data Sheet
31
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
QIMONDA [ QIMONDA AG ]
