HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
The PRECHARGE command is used to deactivate (close) the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t
Care”.
Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row
in that bank, or if the previously open row is already in the process of precharging.
2.4.8.1
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but
without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction
with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or
WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto Precharge is
non persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto
Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time, as described for each burst type.
Table 13
Timing Parameters for PRECHARGE
Parameter
Symbol
- 7.5
Units
ns
Notes
min.
max.
100k
1)
ACTIVE to PRECHARGE command period
WRITE recovery time
tRAS
tWR
tRP
45
14
19
–
–
ns
ns
PRECHARGE command period
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
2.4.8.2
CONCURRENT AUTO PRECHARGE
A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE
command issued to a different bank.
Figure 37 shows a READ with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
to bank m. The READ to bank m will interrupt the READ to bank n, CAS latency later. The precharge to bank n
will begin when the READ to bank m is registered.
Figure 38 shows a READ with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge)
to bank m. The precharge to bank n will begin when the WRITE to bank m is registered. DQM should be pulled
HIGH two clock cycles prior to the WRITE to prevent bus contention.
Figure 39 shows a WRITE with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
to bank m. The precharge to bank n will begin tWR after the new command to bank m is registered. The last valid
data-in to bank n is one clock cycle prior to the READ to bank m.
Figure 40 shows a WRITE with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto
Precharge) to bank m. The precharge to bank n will begin tWR after the WRITE to bank m is registered. The last
valid data-in to bank n is one clock cycle prior to the WRITE to bank m.
Data Sheet
35
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
QIMONDA [ QIMONDA AG ]
