HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
Table 12
Timing Parameters for WRITE
Parameter
Symbol
- 7.5
Units
ns
Notes
min.
max.
DQ and DQM input setup time
DQ input hold time
tIS
tIH
1.5
0.8
0.5
0
—
—
—
ns
ns
tCK
ns
ns
ns
ns
ns
—
—
DQM input hold time
—
DQM write mask latency
tDQW
tRC
—
—
1)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
WRITE recovery time
67
19
45
14
19
—
tRCD
tRAS
tWR
tRP
—
100k
—
PRECHARGE command period
—
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
#,+
T2#$
T72
T20
T2!3
T2#
!#4
./0
72)4%
./0
./0
./0
./0
02%
./0
!#4
#OMMAND
!DDRESS
"A !ꢉ
"A !ꢉ
#OL N
"A !ꢉ
2OW X
2OW B
0RE !LL
!0
$IS
!0
!ꢅꢄ ꢇ!0ꢈ
$1
2OW X
2OW B
0RE "ANK !
$) N
$) Nꢓꢅ
$) Nꢓꢆ
$) Nꢓꢐ
"A !ꢉ #OL N ꢃ BANK !ꢉ COLUMN N
$) N ꢃ $ATA )N TO COLUMN N
ꢃ $ONgT #ARE
"URST ,ENGTH ꢃ ꢏ IN THE CASE SHOWNꢂ
ꢐ SUBSEQUENT ELEMENTS OF $ATA )N ARE PROVIDED IN THE PROGRAMMED ORDER FOLLOWING $) Nꢂ
Figure 25 WRITE Burst (CAS Latency = 2)
Data Sheet
28
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
QIMONDA [ QIMONDA AG ]
