HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
T20
2%!$
./0
./0
./0
02%
"A !
./0
./0
!#4
#OMMAND
!DDRESS
"A !ꢉ
#OL N
"A !ꢉ
2OW A
0RE !LL
!0
!ꢅꢄ
ꢇ!0ꢈ
$IS !0
0RE "ANK !
#,ꢃꢐ
$/ N
$/ Nꢓꢅ
$/ Nꢓꢆ
$/ Nꢓꢐ
$1
ꢃ $ONgT #ARE
"A !ꢉ #OL N ꢃ BANK !ꢉ COLUMN Nꢔ "! !M 2OW ꢃ BANK !ꢉ ROW X
$/ N ꢃ $ATA /UT FROM COLUMN N
"URST ,ENGTH ꢃ ꢏ IN THE CASE SHOWNꢂ
#!3 LATENCY ꢃ ꢐ IN THE CASE SHOWN
ꢐ SUBSEQUENT ELEMENTS OF $ATA /UT ARE PROVIDED IN THE PROGRAMMED ORDER FOLLOWING $/ Nꢂ
Figure 22 READ to PRECHARGE Timing
2.4.6
WRITE
#,+
#+%
#3
ꢇ(IGHꢈ
2!3
#!3
7%
!ꢄꢀ!ꢋ
#!
%NABLE !0
"! ꢃ "ANK !DDRESS
#! ꢃ #OLUMN !DDRESS
!0 ꢃ !UTO 0RECHARGE
!ꢅꢄ
!0
$ISABLE !0
ꢃ $ONgT #ARE
"!ꢄꢉ"!ꢅ
"!
Figure 23 WRITE Command
WRITE bursts are initiated with a WRITE command, as shown in Figure 23. Basic timings for the DQs are shown
in Figure 24; they apply to all write operations.
The starting column and bank addresses are provided with the WRITE command, and Auto Precharge is either
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the
Data Sheet
26
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
QIMONDA [ QIMONDA AG ]
