Internet Data Sheet
HYB39SC128[16/32]9EE
128-MBit Synchronous DRAM
Parameter
Symbol
–6
–7
Unit Note1)2)
PC166–333
PC143–333
Min.
Max.
Min.
Max.
4)
Row Cycle Time
tRC
60
12
1
—
—
—
63
14
1
—
—
—
ns
4)
Activate(a) to Activate(b) Command period
CAS(a) to CAS(b) Command period
Refresh Cycle
tRRD
tCCD
ns
tCK
Refresh Period (4096 cycles)
Data Out Hold Time
tREF
tOH
—
3
64
—
—
3
64
—
ms
ns
Read Cycle
Data Out to Low Impedance Time
Data Out to High Impedance Time
Write Cycle
tLZ
0
3
—
6
0
3
—
7
ns
ns
tHZ
Last Data Input to Precharge
(Write without Auto Precharge)
tWR
2
—
2
—
tCK
1) TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns
2) For proper power-up see the operation section of this data sheet.
3) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter.
4) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of
clock cycles = specified value of timing period (counted in fractions as a whole number)
TABLE 15
AC Timing - Absolute Specifications for –7.5
Parameter
Symbol
–7.5
Unit Note1)2)
PC133–333
Min.
Max.
Clock and Clock Enable
Clock Cycle Time
tCK3
tCK2
tAC3
tAC2
tCH
tCL
7.5
10
1000
1000
5.4
6
ns
CL3
ns
ns
ns
ns
ns
ns
CL2
Access Time from Clock
—
CL33)
CL23)
—
Clock High Pulse Width
Clock Low Pulse Width
Transition Time of Clock
Setup and Hold Times
Input Setup Time
2.5
2.5
0.5
—
—
tT
1
tIS
1.5
1
—
—
—
—
—
7.5
ns
ns
ns
ns
ns
ns
Input Hold Time
tIH
CKE Setup Time
tCKS
tCKH
tRSC
tSB
1.5
1
CKE Hold Time
Mode Register Set-up to Active delay
Power Down Mode Entry Time
15
0
Rev. 1.00, 2006-10
19
10302006-7FCJ-R0SX
QIMONDA [ QIMONDA AG ]
