Internet Data Sheet
HYB39SC128[16/32]9EE
128-MBit Synchronous DRAM
Parameter
Symbol
–7.5
PC133–333
Unit Note1)2)
Min.
Max.
Command Setup Time
Command Hold Time
tCMS
tCMH
tAS
1.5
1
—
—
—
—
ns
ns
ns
ns
Address Set-up Time
1.5
1
Address Hold Time
tAH
Common Parameters
Row to Column Delay Time
Row Precharge Time
4)
4)
4)
4)
4)
tRCD
tRP
tRAS
tRC
tRRD
tCCD
20
20
45
65
15
1
—
ns
ns
ns
ns
ns
tCK
—
Row Active Time
100k
—
Row Cycle Time
Activate(a) to Activate(b) Command period
CAS(a) to CAS(b) Command period
Refresh Cycle
—
—
Refresh Period (4096 cycles)
Data Out Hold Time
tREF
tOH
—
3
64
—
ms
ns
Read Cycle
Data Out to Low Impedance Time
Data Out to High Impedance Time
Write Cycle
tLZ
0
3
—
ns
ns
tHZ
7.5
Last Data Input to Precharge
(Write without Auto Precharge)
tWR
2
—
tCK
1) TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns
2) For proper power-up see the operation section of this data sheet.
3) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter.
4) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of
clock cycles = specified value of timing period (counted in fractions as a whole number)
FIGURE 3
Measurement conditions for tAC and tOH
Rev. 1.00, 2006-10
20
10302006-7FCJ-R0SX
QIMONDA [ QIMONDA AG ]
