Internet Data Sheet
HYB39SC128[16/32]9EE
128-MBit Synchronous DRAM
TABLE 13
DC Characteristics
Parameter
Symbol
Min.
Max.
Unit
Input Leakage Current
II(L)
–5
–5
2.4
—
5
µA
µA
V
Output Leakage Current
IO(L)
VOH
VOL
5
LVTTL Output “H“ Level Voltage (lOUT = -2mA)
LVTTL Output “L“ Level Voltage (lOUT = 2mA)
—
0.4
V
4.2
AC Timing Parameters
TABLE 14
AC Timing - Absolute Specifications for –6/ –7
Parameter
Symbol
–6
–7
Unit Note1)2)
PC166–333
PC143–333
Min.
Max.
Min.
Max.
Clock and Clock Enable
Clock Cycle Time
tCK3
tCK2
tAC3
tAC2
tCH
tCL
6
1000
1000
5
7
1000
1000
5.4
ns
CL3
10
—
—
2
10
—
ns
ns
ns
ns
ns
ns
CL2
Access Time from Clock
CL33)
CL23)
6
—
Clock High Pulse Width
Clock Low Pulse Width
Transition Time of Clock
Setup and Hold Times
Input Setup Time
—
2.5
2.5
0.5
—
—
1
2
—
tT
0.5
1
tIS
1.5
1
—
—
—
—
—
6
1.5
1
—
—
—
—
—
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Hold Time
tIH
CKE Setup Time
tCKS
tCKH
tRSC
tSB
1.5
0.7
12
0
1.5
0.8
14
0
CKE Hold Time
Mode Register Set-up to Active delay
Power Down Mode Entry Time
Command Setup Time
Command Hold Time
Address Set-up Time
Address Hold Time
tCMS
tCMH
tAS
1.5
0.7
1.5
0.7
—
—
—
—
1.5
0.8
1.5
0.8
—
—
—
—
tAH
Common Parameters
Row to Column Delay Time
Row Precharge Time
Row Active Time
4)
4)
4)
tRCD
tRP
18
18
42
—
20
20
42
—
ns
ns
ns
—
—
tRAS
100k
100k
Rev. 1.00, 2006-10
18
10302006-7FCJ-R0SX
QIMONDA [ QIMONDA AG ]
