HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
CAS Latency = 2
CK
CK
Read
BST
NOP
Write
NOP
NOP
Command
Address
BAa, COL n
BAa, COL b
CL=2
tDQSS (min)
DQS
DQ
DI a-b
DOa-n
DM
CAS Latency = 2.5
CK
CK
Read
BST
NOP
NOP
Write
NOP
Command
Address
BAa, COL n
BAa, COL b
CL=2.5
tDQSS (min)
DQS
DQ
DOa-n
Dla-b
DM
DO a-n = data out from bank a, column n
.
DI a-b = data in to bank a, column b
1 subsequent elements of data out appear in the programmed order following DO a-n.
Data In elements are applied following Dl a-b in the programmed order, according to burst length.
Shown with nominal tAC, tDQSCK, and tDQSQ
.
Don’t Care
Figure 15 Read to Write: CAS Latencies (Burst Length = 4 or 8)
Data Sheet
31
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
