HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
3.5.3
Writes
Write bursts are initiated with a Write command, as shown on Figure 17 "Write Command" on Page 34.
The starting column and bank addresses are provided with the Write command, and Auto Precharge is either
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the
completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is
disabled.
During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write
command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS
between the Write command and the first rising edge is known as the write preamble; the Low state on DQS
following the last data-in element is known as the write postamble. The time between the Write command and the
first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of one
clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. tDQSS (min) and
t
DQSS (max)). Figure 18 "Write Burst (Burst Length = 4)" on Page 35 shows the two extremes of tDQSS for a burst
of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS enters
High-Z and any additional input data is ignored.
Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case,
a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge
of clock following the previous Write command. The first data element from the new burst is applied after either
the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
The new Write command should be issued x cycles after the first Write command, where x equals the number of
desired data element pairs (pairs are required by the 2n prefetch architecture). Figure 19 "Write to Write (Burst
Length = 4)" on Page 36 shows concatenated bursts of 4. An example of non-consecutive Writes is shown on
Figure 20 "Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4)" on Page 37. Full-speed random
write accesses within a page or pages can be performed as shown on Figure 21 "Random Write Cycles (Burst
Length = 2, 4 or 8)" on Page 38. Data for any Write burst may be followed by a subsequent Read command. To
follow a Write without truncating the write burst, tWTR (Write to Read) should be met as shown on Figure 22 "Write
to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)" on Page 39.
Data for any Write burst may be truncated by a subsequent Read command, as shown in the figures on Figure 23
"Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)" on Page 40 to Figure 25 "Write to Read:
Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)" on Page 42. Note that only the data-in pairs
that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be
masked with DM, as shown in the diagrams noted previously.
Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without
truncating the write burst, tWR should be met as shown on Figure 26 "Write to Precharge: Non-Interrupting
(Burst Length = 4)" on Page 43.
Data for any Write burst may be truncated by a subsequent Precharge command, as shown in the figures on
Figure 27 "Write to Precharge: Interrupting (Burst Length = 4 or 8)" on Page 44 to Figure 29 "Write to
Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length = 4 or 8)" on Page 46. Note that only the
data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data
in should be masked with DM. Following the Precharge command, a subsequent command to the same bank
cannot be issued until tRP is met.
In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as
described above) provides the same operation that would result from the same burst with Auto Precharge. The
disadvantage of the Precharge command is that it requires that the command and address busses be available at
the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to
truncate bursts.
Data Sheet
33
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
