HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
CAS Latency = 2
CK
CK
Read
NOP
NOP
Read
NOP
NOP
Command
Address
BAa, COL n
BAa, COL b
CL=2
DQS
DQ
DO a-n
DOa- b
CAS Latency = 2.5
CK
CK
Read
NOP
NOP
Read
NOP
NOP
NOP
Command
Address
BAa, COL n
BAa, COL b
CL=2.5
DQS
DQ
DO a-n
DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).
Shown with nominal tAC, tDQSCK, and tDQSQ
.
Don’t Care
Figure 12 Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)
Data Sheet
28
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW