HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Electrical Characteristics
4.4
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.)
Notes:
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal
reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full
voltage range specified.
3. Figure 37 represents the timing reference load used in defining the relevant timing parameters of the part. It
is not intended to be either a precise representation of the typical system environment nor a depiction of the
actual load presented by a production tester. System designers will use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers will correlate to their production
test conditions (generally a coaxial transmission line terminated at the tester electronics).
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is
still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for
the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is
1 V/ns in the range between VIL(AC) and VIH(AC)
.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal
does not ring back above (below) the DC input LOW (HIGH) level).
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR
SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the
latest JEDEC specification for DDR components.
VTT
50 Ω
Output
Timing Reference Point
(VOUT
)
30 pF
Figure 37 AC Output Load Circuit Diagram / Timing Reference Load
Data Sheet
60
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
