HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 19
AC Operating Conditions1)
Parameter
Symbol
Values
Max.
Unit Note/
Test
Min.
Condition
2)3)
Input High (Logic 1) Voltage, DQ, DQS and DM Signals VIH(AC)
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals VIL(AC)
V
REF + 0.31 —
V
2)3)
—
V
V
REF – 0.31 V
2)3)4)
2)3)5)
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
VID(AC)
VIX(AC)
0.7
DDQ + 0.6
V
V
0.5 × VDDQ 0.5 × VDDQ
– 0.2 + 0.2
1) VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR200 - DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400);
0 °C ≤ TA ≤ 70 °C
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until VREF stabilizes.
4) VID is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the
same.
Table 20
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition 1)
DDR333
Min.
Min.
Max.
Max.
2)3)4)5)
DQ output access time from
CK/CK
tAC
–0.5
+0.5
–0.7
+0.7
ns
2)3)4)5)
CK high-level width
Clock cycle time
tCH
tCK
0.45
5
0.55
8
0.45
6
0.55
12
tCK
ns
ns
ns
CL = 3.0
2)3)4)5)
6
12
6
12
CL = 2.5
2)3)4)5)
7.5
12
7.5
0.45
12
CL = 2.0
2)3)4)5)
2)3)4)5)
CK low-level width
tCL
0.45
0.55
0.55
tCK
tCK
2)3)4)5)6)
Auto precharge write recovery tDAL
(tWR/tCK)+(tRP/tCK)
+ precharge time
2)3)4)5)
DQ and DM input hold time
tDH
0.4
—
0.45
1.75
—
—
ns
ns
2)3)4)5)6)
DQ and DM input pulse width tDIPW
1.75
—
(each input)
2)3)4)5)
2)3)4)5)
DQS output access time from tDQSCK
CK/CK
–0.6
+0.6
—
–0.6
0.35
—
+0.6
—
ns
DQS input low (high) pulse
width (write cycle)
tDQSL,H 0.35
tCK
DQS-DQ skew (DQS and
associated DQ signals)
tDQSQ
—
—
+0.40
+0.40
+0.40 ns
+0.45 ns
TFBGA
2)3)4)5)
—
TSOPII
2)3)4)5)
Data Sheet
61
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
