HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 20
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition 1)
DDR333
Min.
12
Min.
Max.
Max.
2)3)4)5)
Active bank A to Active bank B tRRD
10
—
—
ns
command
2)3)4)5)
Write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
—
0.25
0
—
tCK
2)3)4)5)10)
Write preamble setup time
Write postamble
—
—
ns
2)3)4)5)11)
0.40
15
2
0.60
—
0.40
15
1
0.60
—
tCK
2)3)4)5)
Write recovery time
ns
2)3)4)5)
Internal write to read command tWTR
—
—
tCK
delay
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
tXSRD
75
—
—
75
—
—
ns
2)3)4)5)
Exit self-refresh to read
command
200
200
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VIH(ac) and VIL(ac)
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW at this time, depending on tDQSS
.
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
Table 21
AC Timing - Absolute Specifications PC2100A and PC2100
Symbol –7 –7F
DDR266
Parameter
Unit Note/
Test Condition
DDR266A
1)
Min. Max.
–0.75 +0.75
0.45 0.55
Min. Max.
–0.75 +0.75
0.45 0.55
2)3)4)5)
2)3)4)5)
DQ output access time from CK/CK
CK high-level width
Clock cycle time
tAC
ns
tCK
ns
ns
tCK
tCH
tCK2
tCK2.5
tCL
7.5
7.5
12
12
7.5
7.5
12
12
CL = 2.0 2)3)4)5)
CL = 2.5 2)3)4)5)
Clock cycle time
2)3)4)5)
CK low-level width
0.45 0.55
0.45 0.55
Data Sheet
63
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
