Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
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TABLE 16
EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010B)
Field Bits
Type1)
Description
BA
[15:14]
w
Bank Adress
00B BA MRS
01B BA EMRS(1)
10B BA EMRS(2)
11B BA EMRS(3): Reserved
SRF
7
w
Address Bus, High Temperature Self Refresh Rate for TCASE > 85°C
0B
1B
A7 disable
A7 enable 2)
A
[6:4]
3
w
w
Address Bus
000B A Address bits
DCC
Address Bus, Duty Cycle Correction (DCC)
0B
1B
A3 DCC disabled
A3 DCC enabled
Partial Self Refresh for 4 banks
PASR [2:0]
w
Address Bus, Partial Array Self Refresh for 4 Banks3)
Note: Only for 256 Mbit and 512 Mbit components
000B PASR0 Full Array
001B PASR1 Half Array (BA[1:0]=00, 01)
010B PASR2 Quarter Array (BA[1:0]=00)
011B PASR3 Not defined
100B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101B PASR5 Half array (BA[1:0]=10, 11)
110B PASR6 Quarter array (BA[1:0]=11)
111B PASR7 Not defined
1) w = write only
2) When DRAM is operated at 85 °C ≤ TCase ≤ 95 °C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
Rev. 1.3, 2007-05
18
07182006-DD60-22E6
QIMONDA [ QIMONDA AG ]
