Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 21
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1) CKE
Previous Cycle6)
Command (N)2) 3)
RAS, CAS, WE
Action (N)2)
Note4)5)
Current Cycle6)
(N)
(N-1)
7)8)11)
Power-Down
Self Refresh
L
L
L
L
H
H
L
H
L
H
L
L
X
Maintain Power-Down
Power-Down Exit
7)9)10)11)
8)11)12)
DESELECT or NOP
X
Maintain Self Refresh
Self Refresh Exit
9)11)12)13)14)
7)9)10)11)15)
9)10)11)15)
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
Bank(s) Active
All Banks Idle
Active Power-Down Entry
Precharge Power-Down
Entry
7)11)14)16)
17)
H
H
L
AUTOREFRESH
Self Refresh Entry
Any State other
than
H
Refer to the Command Truth Table
listed above
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
4) CKE must be maintained HIGH while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh
requirements
8) “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 × tCK + tIH.
12) VREF must be maintained during Self Refresh operation.
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read
commands may be issued only after tXSRD (200 clocks) is satisfied.
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or
Refresh operations are in progress.
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
TABLE 22
Data Mask (DM) Truth Table
Name (Function)
DM
DQs
Note
1)
Write Enable
L
Valid
X
1)
Write Inhibit
H
1) Used to mask write data; provided coincident with the corresponding data.
Rev. 1.3, 2007-05
22
07182006-DD60-22E6
QIMONDA [ QIMONDA AG ]
