UH
JꢍꢌD
GGUꢌ
0
3
%
7ꢀ
ꢃꢀꢀꢌ
Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
%
$
ꢈꢌ %
$
ꢅꢌ %
$
ꢀꢌ $
ꢅ
ꢆꢌ $
ꢅ
ꢈꢌ
$
ꢅꢅ
ꢌ
$
ꢅ
ꢀꢌ
$
ꢉꢌ
$
ꢊꢌ
$
ꢇꢌ
ꢀꢌ
$ꢂꢌ
$
ꢁꢌ
$
ꢃꢌ
$
ꢆꢌ
$ꢈꢌ
$
ꢅꢌ
$ꢀꢌ
ꢀꢌ
ꢅꢌ
ꢅꢌ
TABLE 17
EMR(3) Programming Extended Mode Register Definition(BA[2:0]=011B)
Field
Bits
Type1)
Description
BA2
16
reg.addr
Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
0B
BA2 Bank Address
BA1
BA0
A
15
Bank Adress[1]
1B
BA1 Bank Address
14
Bank Adress[0]
1B
BA0 Bank Address
[13:0]
w
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
00000000000000BA[13:0] Address bits
1) w = write only
TABLE 18
ODT Truth Table
Input Pin
EMRS(1) Address Bit A10
EMRS(1) Address Bit A11
×8 Components
DQ[7:0]
DQS
X
X
0
DQS
X
1
1
0
RDQS
X
0
RDQS
DM
X
×16 Components
DQ[7:0]
DQ[15:8]
LDQS
X
X
X
0
LDQS
X
X
UDQS
X
0
UDQS
LDM
X
X
UDM
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
Rev. 1.3, 2007-05
19
07182006-DD60-22E6
QIMONDA [ QIMONDA AG ]
