Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
2.3
256-Mbit DDR2 Addressing
This chapter describes the 256-Mbit DDR2 addressing.
TABLE 12
DDR2 Addressing for ×8 Organization
Configuration
32Mb x 81)
Note
Bank Address
BA[1:0]
4
Number of Banks
Auto-Precharge
A10 / AP
A[12:0]
A[9:0]
10
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
2)
3)
8
Page Size [Bytes]
1024 (1K)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
TABLE 13
DDR2 Addressing for ×16 Organization
Configuration
16Mb x 161)
Note
Bank Address
BA[1:0]
4
Number of Banks
Auto-Precharge
A10 / AP
A[12:0]
A[8:0]
9
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
2)
3)
16
Page Size [Bytes]
1024 (1K)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
Rev. 1.3, 2007-05
14
07182006-DD60-22E6
QIMONDA [ QIMONDA AG ]
