Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
FIGURE 4
Differential DC and AC Input and Output Logic Levels Diagram
VDDQ
VTR
VCP
Crossing Point
VID
VIX or VOX
VSSQ
SSTL18_3
5.4
Output Buffer Characteristics
This chapter describes the Output Buffer Characteristics.
TABLE 28
SSTL_18 Output DC Current Drive
Symbol
Parameter
SSTL_18
Unit
Note
1)2)
IOH
IOL
Output Minimum Source DC Current
Output Minimum Sink DC Current
–13.4
13.4
mA
mA
2)3)
1)
VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT–VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and VDDQ – 280 mV.
2) The values of IOH(dc) and IOL(dc) are based on the conditions given in 1) and 3). They are used to test drive current capability to ensure VIH.MIN
plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by
shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement.
.
3)
VDDQ = 1.7 V; VOUT
=
280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
TABLE 29
SSTL_18 Output AC Test Conditions
Symbol
Parameter
SSTL_18
Unit
Note
1)
VOH
VOL
Minimum Required Output Pull-up
VTT + 0.603
VTT – 0.603
0.5 × VDDQ
V
V
V
1)
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
VOTR
1) SSTL_18 test load for VOH and VOL is different from the referenced load. The SSTL_18 test load has a 20 Ohm series resistor additionally
to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that ± 335 mV must be developed across the effectively 25
Ohm termination resistor (13.4 mA x 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum
requirement of 603 mV swing relative to VTT, at the ouput device (13.4 mA x 45 Ohm = 603 mV).
Rev. 1.11, 2006-09
27
03292006-PJAE-UQLG
QIMONDA [ QIMONDA AG ]
