Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS (and RDQS) signals are internally
disabled and don’t care.
relative to the rising or falling edges of DQS crossing at VREF
.
TABLE 25
DC & AC Logic Input Levels
Symbol
Parameter
DDR2-400, DDR2-533
Min. Max.
DDR2-667
Min.
Unit
Max.
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
DC input logic high
DC input low
V
REF + 0.125
V
V
DDQ + 0.3
REF – 0.125
V
REF + 0.125
V
V
DDQ + 0.3
REF – 0.125
V
V
V
V
–0.3
–0.3
AC input logic high
AC input low
VREF + 0.250
—
V
REF + 0.200
—
—
V
REF – 0.250
—
VREF – 0.200
TABLE 26
Single-ended AC Input Test Conditions
Symbol
Condition
Value
Unit
Note
1)
VREF
Input reference voltage
0.5 × VDDQ
1.0
V
1)
VSWING.MAX
SLEW
Input signal maximum peak to peak swing
Input signal minimum Slew Rate
V
2)3)
1.0
V / ns
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to
IL(ac).MAX for falling edges as shown in Figure 3
V
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative
transitions.
Rev. 1.11, 2006-09
25
03292006-PJAE-UQLG
QIMONDA [ QIMONDA AG ]
