Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
FIGURE 3
Single-ended AC Input Test Conditions Diagram
9''4
9,+ꢎDFꢏPLQ
9,+ꢎGFꢏPLQ
95()
96:,1*ꢎ0$;ꢏ
9,/ꢎGFꢏPD[
9,/ꢎDFꢏPD[
966
'HOWDꢌ7)
'HOWDꢌ75
95()ꢌꢐꢌ9,/ꢎDFꢏPD[
'HOWDꢌ7)
9,+ꢎDFꢏPLQꢌꢐꢌ95()
)DOOLQJꢌ6OHZꢌ
5LVLQJꢌ6OHZꢌ
'HOWDꢌ75
03(7ꢀꢅꢁꢀ
TABLE 27
Differential DC and AC Input and Output Logic Levels
Symbol
Parameter
DC input signal voltage
Min.
Max.
Unit
Note
1)
2)
3)
4)
5)
VIN(dc)
VID(dc)
VID(ac)
VIX(ac)
VOX(ac)
–0.3
V
V
V
DDQ + 0.3
—
—
V
DC differential input voltage
0.25
DDQ + 0.6
DDQ + 0.6
AC differential input voltage
0.5
AC differential cross point input voltage
0.5 × VDDQ – 0.175
0.5 × VDDQ + 0.175
0.5 × VDDQ + 0.125
V
AC differential cross point output voltage 0.5 × VDDQ – 0.125
V
1)
2)
3)
V
V
V
IN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
ID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc)
ID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac)
.
.
4) The value of VIX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)
indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)
indicates the voltage at which differential input signals must cross.
Rev. 1.11, 2006-09
26
03292006-PJAE-UQLG
QIMONDA [ QIMONDA AG ]
