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HYB18TC1G800AF 参数 Datasheet PDF下载

HYB18TC1G800AF图片预览
型号: HYB18TC1G800AF
PDF下载: 下载PDF文件 查看货源
内容描述: 1千兆位DDR2 SDRAM [1-Gbit DDR2 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 54 页 / 3010 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18TC1G[80/16]0AF  
1-Gbit DDR2 SDRAM  
7.2  
AC Timing Parameters  
List of Timing Parameters Tables.  
Table 40 “Timing Parameter by Speed Grade - DDR2–667” on Page 37  
Table 41 “Timing Parameter by Speed Grade - DDR2–533” on Page 42  
Table 42 “Timing Parameter by Speed Grade - DDR2-400” on Page 44  
TABLE 40  
Timing Parameter by Speed Grade - DDR2–667  
Parameter  
Symbol  
DDR2–667  
Unit  
Note  
1)2)3)4)5)6)7)  
Min.  
Max.  
8)  
DQ output access time from CK / CK  
DQS output access time from CK / CK  
Average clock high pulse width  
Average clock low pulse width  
Average clock period  
tAC  
–450  
–400  
0.48  
0.48  
3000  
100  
+450  
+400  
0.52  
0.52  
8000  
ps  
8)  
tDQSCK  
tCH.AVG  
tCL.AVG  
tCK.AVG  
tDS.BASE  
tDH.BASE  
ps  
9)10)  
9)10)  
tCK.AVG  
tCK.AVG  
ps  
11)12)13)  
12)13)14)  
DQ and DM input setup time  
DQ and DM input hold time  
ps  
175  
ps  
Control & address input pulse width for each input tIPW  
0.6  
tCK.AVG  
tCK.AVG  
ps  
DQ and DM input pulse width for each input  
Data-out high-impedance time from CK / CK  
DQS/DQS low-impedance time from CK / CK  
DQ low impedance time from CK/CK  
tDIPW  
tHZ  
tLZ.DQS  
tLZ.DQ  
0.35  
8)15)  
8)15)  
8)15)  
16)  
tAC.MAX  
tAC.MAX  
tAC.MAX  
240  
tAC.MIN  
2 × tAC.MIN  
ps  
ps  
DQS-DQ skew for DQS & associated DQ signals tDQSQ  
ps  
17)  
CK half pulse width  
tHP  
Min(tCH.ABS  
,
ps  
tCL.ABS  
)
18)  
19)  
DQ hold skew factor  
tQHS  
tQH  
340  
ps  
DQ/DQS output hold time from DQS  
t
HP tQHS  
ps  
Write command to DQS associated clock edges WL  
RL–1  
nCK  
tCK.AVG  
20)  
DQS latching rising transition to associated clock tDQSS  
– 0.25  
+ 0.25  
edges  
DQS input high pulse width  
DQS input low pulse width  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
Write postamble  
tDQSH  
tDQSL  
tDSS  
0.35  
0.35  
0.2  
tCK.AVG  
tCK.AVG  
tCK.AVG  
tCK.AVG  
tCK.AVG  
tCK.AVG  
ps  
20)  
20)  
tDSH  
0.2  
tWPST  
tWPRE  
tLS.BASE  
tLH.BASE  
tRPRE  
tRPST  
tRAS  
0.4  
0.6  
Write preamble  
0.35  
200  
275  
0.9  
21)22)  
22)23)  
24)25)  
24)26)  
27)  
Address and control input setup time  
Address and control input hold time  
Read preamble  
ps  
1.1  
0.6  
70000  
tCK.AVG  
tCK.AVG  
ns  
Read postamble  
0.4  
Active to precharge command  
45  
Rev. 1.11, 2006-09  
37  
03292006-PJAE-UQLG  
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