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HYB18TC1G800AF 参数 Datasheet PDF下载

HYB18TC1G800AF图片预览
型号: HYB18TC1G800AF
PDF下载: 下载PDF文件 查看货源
内容描述: 1千兆位DDR2 SDRAM [1-Gbit DDR2 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 54 页 / 3010 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18TC1G[80/16]0AF  
1-Gbit DDR2 SDRAM  
7
Timing Characteristics  
This chapter contains speed grade definition, AC timing parameter and ODT tables.  
7.1  
Speed Grade Definitions  
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications (tCK = 5ns with tRAS = 40ns).  
List of Speed Grade Definition tables:  
Table 37 “Speed Grade Definition Speed Bins for DDR2–667D” on Page 34  
Table 38 “Speed Grade Definition Speed Bins for DDR2–533C” on Page 35  
Table 39 “Speed Grade Definition Speed Bins for DDR2–400B” on Page 36  
TABLE 37  
Speed Grade Definition Speed Bins for DDR2–667D  
Speed Grade  
DDR2–667D  
Unit  
Note  
IFX Sort Name  
–3S  
CAS-RCD-RP latencies  
5–5–5  
Min.  
tCK  
Parameter  
Symbol  
Max.  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
tCK  
5
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
3.75  
3
8
tCK  
8
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
Row Precharge Time  
tRAS  
tRC  
tRCD  
tRP  
45  
60  
15  
15  
70000  
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal  
OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements” .  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,  
input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,  
RDQS / RDQS is defined.  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.  
4) The output timing reference voltage level is VTT  
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI  
t
.
Rev. 1.11, 2006-09  
34  
03292006-PJAE-UQLG  
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