1&ꢀ
'
46ꢀ
6ꢀ
64ꢀ
64ꢀ
6ꢀ
&.(ꢀ
:
(ꢀ
5$6ꢀ
&$6ꢀ
$ꢂꢀ
2'7ꢀ
6''ꢀ
666ꢀ
$ꢃ
3ꢀ $ꢃꢀ
$ꢇꢀ
6ꢀ
$ꢃ
1&ꢀ
1&ꢀ 1&
ꢌ
ꢃꢅꢀ
ꢂꢀ
$
0
3
3
7ꢁ
ꢁꢂꢁꢀ
Internet Data Sheet
HYB18T512[40/80/16]0B[C/F]
512-Mbit Double-Data-Rate-Two SDRAM
FIGURE 1
Chip Configuration for ×4 components, PG-TFBGA-60 (top view)
ꢃꢀ
ꢂꢀ
ꢅꢀ
66
ꢊꢀ
ꢇꢀ
$ꢀ
%ꢀ
&ꢀ
'ꢀ
(ꢀ
)ꢀ
*ꢀ
+ꢀ
-ꢀ
ꢉꢀ
ꢆꢀ
ꢋꢀ
ꢈꢀ
6''ꢀ
6664ꢀ
6''4ꢀ
66
6664ꢀ
1&ꢀ
'0ꢀ
'46ꢀ
1&ꢀ
6''4ꢀ
6''4ꢀ
6''4ꢀ
6''4ꢀ
'4ꢃꢀ
'4ꢁꢀ
66
6664ꢀ
1&ꢀ
'4ꢅꢀ
'4ꢂꢀ
1&ꢀ
6''/ꢀ 65()ꢀ
66
6''ꢀ
9ꢀ
&.ꢀ
&.ꢀ
&6ꢀ
$ꢁꢀ
$ꢊꢀ
$ꢋꢀ
66'/ꢀ
1&ꢀ
%$ꢁꢀ
ꢁꢄ$
%$ꢃꢀ
66
$ꢅꢀ
$ꢆꢀ
$ꢉꢀ
.ꢀ
/ꢀ
$ꢈꢀ
$ꢃꢃꢀ
6''ꢀ
Notes
1. VDDL and VSSDL are power and ground for the DLL. VDDL is
2. Ball position L8 is A13 for 512-Mbit and is Not Connected
on 256-Mbit
connected to VDD on the device. VDD, VDDQ, VSSDL, VSS
,
and VSSQ are isolated on the device.
Rev. 1.1, 2007-05
13
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
