Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
4
Truth Tables
TABLE 12
Command Truth Table
Function
CKE
CS RAS CAS WE BA0 A[13:11] A10 A[9:0]
Note1)2)3)
BA1
Previous Current
Cycle
Cycle
4)5)
(Extended) Mode
Register Set
H
H
L
L
L
L
BA
OP Code
4)
Auto-Refresh
H
H
L
H
L
L
L
H
L
L
L
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
4)6)
4)6)7)
Self-Refresh Entry
Self-Refresh Exit
L
L
H
X
H
L
X
H
H
H
H
L
4)5)
4)
Single Bank Precharge
Precharge all Banks
Bank Activate
H
H
H
H
H
H
H
H
H
H
BA
X
X
X
L
X
X
L
L
H
4)5)
4)5)8)
4)5)8)
L
H
L
BA
BA
BA
Row Address
Write
H
H
Column
Column
L
Column
Column
Write with Auto-
Precharge
L
L
H
4)5)8)
4)5)8)
Read
H
H
H
H
L
L
H
H
L
L
H
H
BA
BA
Column
Column
L
Column
Column
Read with Auto-
Precharge
H
4)
No Operation
H
H
H
X
X
L
L
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
4)
Device Deselect
Power Down Entry
H
H
L
4)9)
4)9)
Power Down Exit
L
H
H
L
X
X
X
X
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register.
6)
VREF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated.
9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements.
Rev. 1.43, 2006-11
16
03292006-L40N-L04G
QIMONDA [ QIMONDA AG ]
